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general description the max8716/max8717/max8757 are dual, step- down, interleaved, fixed-frequency, switch-mode power-supply (smps) controllers with synchronous rec- tification. they are intended for main (5v/3.3v) and i/o power generation in battery-powered systems. fixed-frequency operation with optimal interleaving minimizes input ripple current from the lowest input volt- ages up to the 26v maximum input. optimal 40/60 inter- leaving allows the input voltage to go down to 8.3v before duty-cycle overlap occurs, compared to 180 out-of-phase regulators where the duty-cycle overlap occurs when the input drops below 10v. accurate output current limit is achieved using a sense resistor. alternatively, power dissipation can be reduced using lossless inductor current sensing. independent on/off controls and power-good signals allow flexible power sequencing. soft-start reduces inrush current, while soft-stop gradually ramps the out- put voltage down preventing negative voltage dips. a low-noise mode maintains high light-load efficiency while keeping the switching frequency out of the audi- ble range. the max8716 is available in a 24-pin thin qfn pack- age, and the max8717/max8757 are available in a 28- pin thin qfn package. applications 2 to 4 li+ cell battery-powered devices notebook and subnotebook computers pdas and mobile communicators main or i/o power supplies features ? fixed 200khz, 300khz, or 500khz switching frequency ? no current-sense resistor required ? 40/60 optimal interleaving ? reduced input-capacitor requirement ? 3.3v and 5v fixed or 1.0v to 5.5v adjustable outputs (dual mode?) ? 4v to 26v input range ? independently selectable pwm, skip, and low- noise mode operation ? soft-start and soft-stop ? 2v precision reference with 0.75% accuracy ? independent power-good outputs max8716/max8717/max8757 interleaved high-efficiency, dual power-supply controllers for notebook computers ________________________________________________________________ maxim integrated products 1 24 23 22 21 20 19 pgood1 fb1 csl1 csh1 bst1 dh1 7 8 9 10 11 12 pgood2 fb2 csl2 csh2 bst2 dh2 13 14 15 16 17 18 lx2 dl2 v dd gnd dl1 lx1 6 5 4 3 2 1 on2 on1 skip2 ref skip1 v cc max8716etg top view 28 27 26 25 24 23 22 8 9 10 11 12 13 14 15 16 17 18 19 20 21 7 6 5 4 3 2 1 max8717eti MAX8757ETI+ tqfn tqfn top view skip1 v cc ref skip2 fsel on1 on2 ilim1 pgood1 fb1 csl1 csh1 bst1 dh1 lx1 dl1 agnd pgnd v dd dl2 lx2 dh2 bst2 csh2 csl2 fb2 pgood2 ilim 2 pin configurations ordering information 19-3569; rev 1; 6/05 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available part temp range pin-package max8716 etg -40? to +85? 24 thin qfn 4mm x 4mm max8716etg+ -40? to +85? 24 thin qfn 4mm x 4mm max8717 eti -40? to +85? 28 thin qfn 5mm x 5mm max8717eti+ -40? to +85? 28 thin qfn 5mm x 5mm max8757 eti+ -40? to +85? 28 thin qfn 5mm x 5mm dual mode is a trademark of maxim integrated products, inc. + denotes lead-free package.
max8716/max8717/max8757 interleaved high-efficiency, dual power-supply controllers for notebook computers 2 _______________________________________________________________________________________ absolute maximum ratings (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd , v cc , csl1, csh1, csl2, csh2 to agnd ......-0.3v to +6v on1, on2, skip1 , skip2 , pgood1, pgood2 to agnd ...............................................-0.3v to +6v fb1, fb2, ilim1, ilim2, fsel to agnd ...................-0.3v to +6v ref to agnd..............................................-0.3v to (v cc + 0.3v) bst1, bst2 to agnd .............................................-0.3v to +36v lx1 to bst1..............................................................-6v to +0.3v lx2 to bst2..............................................................-6v to +0.3v dh1 to lx1 ..............................................-0.3v to (v bst1 + 0.3v) dh2 to lx2 ..............................................-0.3v to (v bst2 + 0.3v) dl1, dl2 to pgnd .....................................-0.3v to (v dd + 0.3v) agnd to pgnd .....................................................-0.3v to +0.3v ref short circuit to agnd.........................................continuous ref current ......................................................................+10ma continuous power dissipation (t a = +70?) 24-pin thin qfn 4mm x 4mm (derate 20.8mw/? above +70?)..........................................................1666.7mw 28-pin thin qfn 5mm x 5mm (derate 21.3mw/? above +70?)..........................................................1702.1mw operating temperature range ...........................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? electrical characteristics (circuit of figure 1, v in = 12v, fsel = ref, skip_ = 0, v on_ = v ilim_ = v cc = v dd = 5v , t a = 0c to +85c , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units input supplies v in 26 input voltage range v bias v cc , v dd 4.5 5.5 v v cc rising 3.9 4.15 4.4 v cc undervoltage-lockout threshold v uvlo 200mv typical hysteresis v cc falling 3.7 3.95 4.2 v quiescent supply current (v cc )i cc csl_ and fb_ forced above their regulation points 0.8 1.3 ma quiescent supply current (v dd )i dd csl_ and fb_ forced above their regulation points <1 5 a shutdown supply current (v cc ) on1 = on2 = gnd <1 5 a shutdown supply current (v dd ) on1 = on2 = gnd <1 5 a main smps controllers pwm1 output voltage in fixed mode v out1 v in = 6v to 26v, skip1 = v cc , zero to full load (note 2) 3.265 3.30 3.365 v pwm2 output voltage in fixed mode v out2 v in = 6v to 26v, skip2 = v cc , zero to full load (note 2) 4.94 5.00 5.09 v v in = 6v to 26v, fb1 or fb2, duty factor = 20% to 80% 0.990 1.005 1.020 feedback voltage in adjustable mode (note 2) v fb_ v in = 6v to 26v, fb1 or fb2, duty factor = 50% 0.995 1.005 1.015 v output-voltage adjust range either smps 1.0 5.5 v fb1, fb2 fixed-mode threshold voltage dual-mode comparator 1.9 2.1 v feedback input leakage current fb1 = 1.1v, fb2 = 1.1v -0.1 +0.1 ? dc load regulation either smps, skip_ = v cc , zero to full load -0.1 % note 1: for the 24-pin tqfn version, agnd and pgnd refer to a single pin designated gnd.
max8716/max8717/max8757 interleaved high-efficiency, dual power-supply controllers for notebook computers _______________________________________________________________________________________ 3 electrical characteristics (continued) (circuit of figure 1, v in = 12v, fsel = ref, skip_ = 0, v on_ = v ilim_ = v cc = v dd = 5v , t a = 0c to +85c , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units line-regulation error either smps, 4v < v in < 26v 0.03 %/v fb_ input bias current i fb_ v fb_ = 0 to 5.5v -0.1 +0.1 ? fsel = gnd 170 200 230 fsel = ref (note 3) 270 300 330 khz operating frequency f osc fsel = v cc 425 500 575 fsel = gnd 97.5 99 fsel = ref (note 3) 97.5 99 maximum duty factor d max fsel = v cc 97.5 99 % minimum on-time t on ( min ) (note 4) 200 ns 40 % smps1 to smps2 phase shift smps2 starts after smps1 144 degrees soft-start ramp time t sstart measured from the rising edge of on_ to full scale, ref = 2v 2ms soft-stop ramp time t sstop measured from the falling edge of on_ to full scale 4ms current limit ilim_ adjustment range 0.5 v ref v current-limit threshold (fixed) v limit _ v csh _ - v csl _, ilim_ = v cc (note 3) 45 50 55 mv v ilim _ = 2.00v 190 200 210 current-limit threshold (adjustable) v limit _ v csh _ - v csl _ v ilim _ = 1.00v 94 100 106 mv v csh _ - v csl _, skip_ = ilim_ = v cc (note 3) -67 -60 -53 mv current-limit threshold (negative) v neg v csh _ - v csl _, skip_ = v cc , adjustable mode, percent of current limit -120 % current-limit threshold (zero crossing) v zx v csh _ - v csl _, skip_ = gnd or ref 3 mv ilim_ = v cc (note 3) 61014mv idle mode threshold v idle v csh _ - v csl _, skip_ = gnd with respect to current-limit threshold 20 % ilim_ = v cc (note 3) 2.5 5 7.5 mv low-noise mode threshold v ln v csh _ - v csl _ skip_ = ref with respect to current-limit threshold 10 % ilim_ leakage current 0.1 ? reference (ref) t a = +25? to +85? 1.985 2.00 2.015 reference voltage v ref v cc = 4.5v to 5.5v, i ref = 0 t a = 0? to +85? 1.98 2.00 2.02 v idle mode is a trademark of maxim integrated products, inc.
max8716/max8717/max8757 interleaved high-efficiency, dual power-supply controllers for notebook computers 4 _______________________________________________________________________________________ electrical characteristics (continued) (circuit of figure 1, v in = 12v, fsel = ref, skip_ = 0, v on_ = v ilim_ = v cc = v dd = 5v , t a = 0c to +85c , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units reference load regulation ? v ref i ref = 0? to 50? 10 mv reference sink current 10 ? ref lockout voltage v ref ( uvlo ) rising edge, hysteresis = 50mv 1.8 v fault detection output overvoltage trip threshold max8716/max8717 only 11 15 19 % output overvoltage fault- propagation delay t ovp 50mv overdrive, max8716/max8717 only 10 ? output undervoltage-protection trip threshold with respect to error-comparator threshold 65 70 75 % output undervoltage fault- propagation delay t uvp 50mv overdrive 10 ? output undervoltage-protection blanking time t blank from rising edge of on_ 6144 1/f osc pgood_ lower trip threshold with respect to error-comparator threshold, hysteresis = 1% -12.5 -10 -8.0 % pgood_ propagation delay t pgood _ falling edge, 50mv overdrive 10 s pgood_ output low voltage i sink = 4ma 0.4 v pgood_ leakage current i pgood _ high state, pgood_ forced to 5.5v 1 a thermal-shutdown threshold t shdn hysteresis = 15? +160 ? gate drivers dh_ gate-driver on-resistance r dh bst_ - lx_ forced to 5v (note 5) 1.5 5 ? dl_, high state (note 5) 1.7 5 dl_ gate-driver on-resistance r dl dl_, low state (note 5) 0.6 3 ? dh_ gate-driver source/sink current i dh dh_ forced to 2.5v, bst_ - lx_ forced to 5v 2a dl_ gate-driver source current i dl ( source ) dl_ forced to 2.5v 1.7 a dl_ gate-driver sink current i dl ( sink ) dl_ forced to 2.5v 3.3 a dl_ rising 35 dead time t dead dh_ rising 26 ns lx_, bst_ leakage current v bst _ = v lx _ = 26v <2 20 a inputs and outputs logic input current on1, on2 -1 +1 ? on_ input voltage rising edge, hysteresis = 225mv 1.2 1.7 2.2 v high v cc - 0.2 ref 1.7 2.3 tri-level input logic skip1 , skip2 , fsel gnd 0.5 v
max8716/max8717/max8757 interleaved high-efficiency, dual power-supply controllers for notebook computers _______________________________________________________________________________________ 5 parameter symbol conditions min typ max units input leakage current skip1 , skip2 , fsel, 0v, or v cc -3 +3 ? input leakage current ilim1, ilim2, 0v, or v cc -0.1 +0.1 ? input leakage current csh_, 0v, or v dd -0.1 +0.1 ? input bias current csl_, 0v, or v dd 25 50 ? electrical characteristics (continued) (circuit of figure 1, v in = 12v, fsel = ref, skip_ = 0, v on_ = v ilim_ = v cc = v dd = 5v , t a = 0c to +85c , unless otherwise noted. typical values are at t a = +25?.) electrical characteristics (circuit of figure 1, v in = 12v, fsel = ref, skip_ = 0, v on_ = v ilim_ = v cc = v dd = 5v, t a = -40c to +85c, unless otherwise noted.) (note 6) parameter symbol conditions min typ max units input supplies v in 26 input voltage range v bias v cc , v dd 4.5 5.5 v quiescent supply current (v cc )i cc csl_ and fb_ forced above their regulation points 1.3 ma quiescent supply current (v dd )i dd csl_ and fb_ forced above their regulation points 5a shutdown supply current (v cc ) on1 = on2 = gnd 5 a shutdown supply current (v dd ) on1 = on2 = gnd 5 a main smps controllers pwm1 output voltage in fixed mode v out1 v in = 6v to 26v, skip1 = v cc , zero to full load (note 1) 3.255 3.375 v pwm2 output voltage in fixed mode v out2 v in = 6v to 26v, skip2 = v cc , zero to full load (note 1) 4.925 5.105 v feedback voltage in adjustable mode v fb_ v in = 6v to 26v, fb1 or fb2, duty factor = 20% to 80% (note 1) 0.987 1.023 v output voltage adjust range either smps 1.0 5.5 v fb1, fb2 fixed-mode threshold voltage dual-mode comparator 1.9 2.1 v fsel = gnd 170 230 fsel = ref (note 3) 270 330 khz operating frequency f osc fsel = v cc 425 575 fsel = gnd 97.5 fsel = ref (note 3) 97.5 maximum duty factor d max fsel = v cc 97.5 % minimum on-time t on ( min ) (note 4) 200 ns current limit ilim_ adjustment range 0.5 v ref v
max8716/max8717/max8757 interleaved high-efficiency, dual power-supply controllers for notebook computers 6 _______________________________________________________________________________________ electrical characteristics (continued) (circuit of figure 1, v in = 12v, fsel = ref, skip_ = 0, v on_ = v ilim_ = v cc = v dd = 5v, t a = -40c to +85c, unless otherwise noted.) (note 6) parameter symbol conditions min typ max units current-limit threshold (fixed) v limit _ v csh _ - v csl _, ilim_ = v cc (note 3) 44 56 mv v ilim _ = 2.00v 188 212 current-limit threshold (adjustable) v limit _ v csh _ - v csl _ v ilim _ = 1.00v 93 107 mv reference (ref) reference voltage v ref v cc = 4.5v to 5.5v, i ref = 0 1.98 2.02 v fault detection output overvoltage trip threshold max8716/max8717 only 11 19 % output undervoltage-protection trip threshold with respect to error-comparator threshold 65 75 % pgood_ lower trip threshold with respect to error-comparator threshold, hysteresis = 1% -12.5 -8.0 % pgood_ output low voltage i sink = 4ma 0.4 v gate drivers dh_ gate-driver on-resistance r dh bst_ - lx_ forced to 5v (note 5) 5 ? dl_, high state (note 5) 5 dl_ gate driver on-resistance r dl dl_, low state (note 5) 3 ? inputs and outputs on_ input voltage rising edge, hysteresis = 225mv 1.2 2.2 v high v cc - 0.2 ref 1.7 2.3 three-level input logic skip1 , skip2 , fsel gnd 0.5 v note 2: when the inductor is in continuous conduction, the output voltage will have a dc regulation level lower than the error-com- parator threshold by 50% of the ripple. in discontinuous conduction, the output voltage will have a dc regulation level high- er than the error-comparator threshold by 50% of the ripple. note 3: default setting for the max8716. note 4: specifications are guaranteed by design, not production tested. note 5: production testing limitations due to package handling require relaxed maximum on-resistance specifications for the thin qfn package. note 6: specifications from 0? to -40? are guaranteed by design, not production tested.
max8716/max8717/max8757 interleaved high-efficiency, dual power-supply controllers for notebook computers _______________________________________________________________________________________ 7 100 50 0.001 0.01 0.1 1 10 3.3v output efficiency vs. load current 60 max8716/17/57 toc01 load current (a) efficiency (%) 70 80 90 v in = 6v skip mode low- noise mode pwm mode 100 50 0.001 0.01 0.1 1 10 3.3v output efficiency vs. load current 60 max8716/17/57 toc02 load current (a) efficiency (%) 70 80 90 v in = 12v skip mode pwm mode low- noise mode 100 50 0.001 0.01 0.1 1 10 3.3v output efficiency vs. load current 60 max8716/17/57 toc03 load current (a) efficiency (%) 70 80 90 v in = 20v skip mode pwm mode low- noise mode 3.3v output voltage vs. load current max8716/17/57 toc04 load current (a) output voltage (v) 4 3 2 1 3.30 3.35 3.40 3.25 05 skip mode pwm mode v in = 12v low- noise mode 100 50 0.001 0.01 0.1 1 10 5v output efficiency vs. load current 60 max8716/17/57 toc05 load current (a) efficiency (%) 70 80 90 pwm mode v in = 6v low- noise mode skip mode 100 50 0.001 0.01 0.1 1 10 5v output efficiency vs. load current 60 max8716/17/57 toc06 load current (a) efficiency (%) 70 80 90 v in = 12v skip mode pwm mode low- noise mode 100 50 0.001 0.01 0.1 1 10 5v output efficiency vs. load current 60 max8716/17/57 toc07 load current (a) efficiency (%) 70 80 90 v in = 20v skip mode pwm mode low- noise mode 5v output voltage vs. load current max8716/17/57 toc08 load current (a) output voltage (v) 4 1 3 2 5.00 5.05 5.10 5.15 4.95 05 skip mode pwm mode v in = 12v low- noise mode 2.5v output efficiency vs. load current max8716/17/57 toc09 load current (a) efficiency (%) 1 0.1 0.01 60 70 80 90 100 50 0.001 10 skip mode pwm mode v in = 12v l = 4.3 h low-noise mode typical operating characteristics (circuit of figure 1, v in = 12v, v dd = v cc = 5v, skip_ = gnd, fsel = ref, t a = +25?, unless otherwise noted.)
max8716/max8717/max8757 interleaved high-efficiency, dual power-supply controllers for notebook computers 8 _______________________________________________________________________________________ typical operating characteristics (continued) (circuit of figure 1, v in = 12v, v dd = v cc = 5v, skip_ = gnd, fsel = ref, t a = +25?, unless otherwise noted.) 1.8v output efficiency vs. load current max8716/17/57 toc10 load current (a) efficiency (%) 1 0.1 0.01 60 70 80 90 100 50 0.001 10 skip mode pwm mode v in = 12v l = 3.2 h low-noise mode no-load supply current vs. input voltage (forced-pwm mode) input voltage (v) supply current (ma) 20 16 12 8 4 4 8 12 16 20 24 28 0 024 max8716/17/57 toc11 i bias i in skip1 = skip2 = v cc on1 = on2 = v cc 0.1 1 10 0.01 no-load supply current vs. input voltage (idle mode) input voltage (v) supply current (ma) 20 16 12 8 4 024 max8716/17/57 toc12 i bias i in skip1 = skip2 = gnd or ref on1 = on2 = v cc out2 idle-mode current vs. input voltage idle-mode current (a) 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0 input voltage (v) 20 16 12 8 4 024 max8716/17/57 toc13 maximum duty- cycle limited skip2 = gnd skip2 = ref out2 switching frequency vs. load current load current (a) switching frequency (khz) 1 0.1 0.01 10 100 1000 1 0.001 10 max8716/17/57 toc14 skip2 = gnd skip2 = ref skip2 = v cc 5v output voltage vs. input voltage output voltage (v) 4.95 5.00 5.05 4.90 input voltage (v) 20 16 12 8 4 024 max8716/17/57 toc15 skip2 = v cc 3.3v output voltage vs. input voltage output voltage (v) 3.30 3.35 3.40 3.25 input voltage (v) 20 16 12 8 4 024 max8716/17/57 toc16 skip1 = v cc dropout voltage (v) 0.1 0.2 0.3 0.4 0 out2 dropout voltage vs. load current load current (a) 4 3 2 1 05 max8716/17/57 toc17 v out2 = 4.8v
startup waveforms max8716/17/57 toc18 400 s/div 0 2v 0 0 0 0 0 a. lx2, 20v/div b. on2, 10v/div c. pgood2, 10v/div d. ref, 2v/div e. out2, 2v/div f. i lx2 , 2.5av/div 1.0 ? load on out2 12v a b c d e f max8716/max8717/max8757 interleaved high-efficiency, dual power-supply controllers for notebook computers _______________________________________________________________________________________ 9 shutdown waveforms max8716/17/57 toc19 1ms/div 2v 0 0 0 a. dl2, 10v/div b. on2, 10v/div c. pgood2, 10v/div d. ref, 2v/div e. out2, 2v/div f. i lx2 , 2.5av/div 5v 5v 5v 5v a b c d e f 1.0k ? load on out2 skip2 = gnd startup waveforms max8716/17/57 toc20 1ms/div 0 0 0 0 0 a. on1/on2, 5v/div b. pgood1, 10v/div c. pgood2, 10v/div d. out2, 2v/div e. out1, 2v/div 3.3v 5v a b c d e v cc uvlo waveforms max8716/17/57 toc21 4ms/div 0 0 a. v cc , 2v/div b. out2, 2v/div c. pgood2, 5v/div d. dl2, 5v/div e. i lx2 , 2.5av/div 5v 5v 5v 5v a b c d e 100 ? load on out2 skip2 = v cc steady-state waveforms max8716/17/57 toc22 2 s/div 0 0 a. out2, 50mv/div b. lx2, 10v/div c. v in , 50mv/div d. out1, 50mv/div e. lx1, 10v/div 5v 12v 12v 3.3v a b c d e 1.0a load on out1, 1.0a load on out2 skip1 = v cc , skip2 = v cc typical operating characteristics (continued) (circuit of figure 1, v in = 12v, v dd = v cc = 5v, skip_ = gnd, fsel = ref, t a = +25?, unless otherwise noted.)
max8716/max8717/max8757 interleaved high-efficiency, dual power-supply controllers for notebook computers 10 ______________________________________________________________________________________ skip1 transition max8716/17/57 toc27 20 s/div 0 a. skip1, 5v/div b. lx1, 10v/div c. out1, 50mv/div d. i lx1 , 2.5a/div 0 0 12v 3.3v 2.5a a b c d 30ma load on out1 dropout waveforms max8716/17/57 toc23 2 s/div 0 0 a. out2, 50mv/div b. lx2, 10v/div c. v in , 50mv/div d. out1, 50mv/div e. lx1, 10v/div 4.9v 5v 5v 5v 3.3v a b c d e 1.0a load on out1, 1.0a load on out2 skip1 = v cc , skip2 = v cc out1 load transient max8716/17/57 toc24 20 s/div 0 0 a. control, 5v/div b. out1, 50mv/div c. i lx1 , 3a/div d. lx1, 10v/div 0 3.3v 3a 12v a b c d skip1 = v cc skip1 transition max8716/17/57 toc25 20 s/div 0 a. skip1, 5v/div b. lx1, 10v/div c. out1, 50mv/div d. i lx1 , 2.5a/div 0 0 12v 3.3v 2.5a a b c d 30ma load on out1 skip1 transition max8716/17/57 toc26 20 s/div 0 a. skip1, 5v/div b. lx1, 10v/div c. out1, 50mv/div d. i lx1 , 2.5a/div 0 0 12v 3.3v 2.5a a b c d 30ma load on out1 typical operating characteristics (continued) (circuit of figure 1, v in = 12v, v dd = v cc = 5v, skip_ = gnd, fsel = ref, t a = +25?, unless otherwise noted.)
max8716/max8717/max8757 interleaved high-efficiency, dual power-supply controllers for notebook computers ______________________________________________________________________________________ 11 pin description pin max8716 max8717/ max8757 name function 11v cc analog supply input. connect to the system supply voltage (+4.5v to +5.5v) through a series 20 ? resistor. bypass v cc to agnd with a 1? or greater ceramic capacitor. 22 skip1 low-noise mode control for smps1. connect skip1 to gnd for normal idle-mode (pulse-skipping) operation or to v cc for pwm mode (fixed frequency). connect to ref for low-noise mode. 3 3 ref 2.0v reference voltage output. bypass ref to agnd with a 0.1? or greater ceramic capacitor. the reference can source up to 50?. loading ref degrades output voltage accuracy according to the ref load-regulation error (see the typical operating characteristics ). the reference shuts down when both on1 and on2 are low. 44 skip2 low-noise mode control for smps2. connect skip2 to gnd for normal idle-mode (pulse-skipping) operation or to v cc for pwm mode (fixed frequency). connect to ref for low-noise mode. 5 fsel frequency select input. this four-level logic input sets the controller? switching frequency. connect fsel to v cc for 500khz, to ref for 300khz, and to gnd for 200khz operation. 5 6 on1 smps1 enable input. drive on1 high to enable smps1. drive on1 low to shut down smps1. 6 7 on2 smps2 enable input. drive on2 high to enable smps2. drive on2 low to shut down smps2. 8 ilim2 smps2 peak current-limit threshold adjustment. connect ilim2 to v cc to enable the default 50mv current-limit threshold. in adjustable mode, the current-limit threshold across csh2 and csl2 is precisely 1/10th the voltage seen at ilim2 over a 500mv to 2.0v range. the logic threshold for switchover to the 50mv default value is approximately v cc - 1v. 7 9 pgood2 smps2 open-drain power-good output. pgood2 is low when smps2 is more than 10% below its regulation threshold, during soft-start, and in shutdown. 8 10 fb2 feedback input for smps2. connect fb2 to v cc for fixed 5v output. in adjustable mode, fb2 regulates to 1v. 9 11 csl2 negative current-sense input for smps2. connect to the negative terminal of the current-sense element. figure 8 describes two different current-sensing options. 10 12 csh2 positive current-sense input for smps2. connect to the positive terminal of the current- sense element. figure 8 describes two different current-sensing options. 11 13 bst2 boost flying capacitor connection for smps2. connect to an external capacitor and diode as shown in figure 1. an optional resistor in series with bst2 allows the dh2 turn- on current to be adjusted. 12 14 dh2 high-side gate-driver output for smps2. dh2 swings from lx2 to bst2. 13 15 lx2 inductor connection for smps2. connect lx2 to the switched side of the inductor. lx2 is the lower supply rail for the dh2 high-side gate driver.
max8716/max8717/max8757 interleaved high-efficiency, dual power-supply controllers for notebook computers 12 ______________________________________________________________________________________ detailed description the max8716/max8717/max8757 standard application circuit (figure 1) generates the 5v/5a and 3.3v/5a typi- cal of the main supplies in notebook computers. the input supply range is 6v to 24v. see table 1 for compo- nent selections, while table 2 lists the compo- nent manufacturers. the max8716/max8717/max8757 contain two inter- leaved fixed-frequency, step-down controllers designed for low-voltage power supplies. the optimal interleaved architecture guarantees out-of-phase oper- ation, which reduces the input capacitor ripple. smps 5v bias supply (v cc and v dd ) the max8716/max8717/max8757 switch-mode power supplies (smps) require a 5v bias supply in addition to the high-power input supply (battery or ac adapter). v dd is the power rail for the mosfet gate drive, and v cc is the power rail for the ic. connect the external 4.5v to 5.5v supply directly to v dd and connect v dd to v cc through an rc filter, as shown in figure 1. the maximum supply current required is: i bias = i cc + f sw (q g(nl1) + q g1(nh1) +q g2(nl2) + q g2(nh2) ) = 1.3ma to 40ma where i cc is 1.3ma, f sw is the switching frequency, and q g_ are the mosfet data sheet? total gate- charge specification limits at v gs = 5v. pin description (continued) pin max8716 max8717/ max8757 name function 14 16 dl2 low-side gate-driver output for smps2. dl2 swings from pgnd to v dd. 15 17 v dd supply voltage input for the dl_ gate drivers. connect to a 5v supply. 16 gnd power and analog ground. connect backside pad to gnd. 18 pgnd power ground 19 agnd analog ground. connect backside pad to agnd. 17 20 dl1 low-side gate-driver output for smps1. dl1 swings from pgnd to v dd. 18 21 lx1 inductor connection for smps1. connect lx1 to the switched side of the inductor. lx1 is the lower supply rail for the dh1 high-side gate driver. 19 22 dh1 high-side gate-driver output for smps1. dh1 swings from lx1 to bst1. 20 23 bst1 boost flying capacitor connection for smps1. connect to an external capacitor and diode as shown in figure 1. an optional resistor in series with bst1 allows the dh1 turn- on current to be adjusted. 21 24 csh1 positive current-sense input for smps1. connect to the positive terminal of the current- sense element. figure 8 describes two different current-sensing options. 22 25 csl1 negative current-sense input for smps1. connect to the negative terminal of the current-sense element. figure 8 describes two different current-sensing options. 23 26 fb1 feedback input for smps1. connect fb1 to v cc for fixed 3.3v output. in adjustable mode, fb1 regulates to 1v. 24 27 pgood1 smps1 open-drain power-good output. pgood1 is low when smps1 is more than 10% below its regulation threshold, during soft-start, and in shutdown. 28 ilim1 smps1 peak current-limit threshold adjustment. connect ilim1 to v cc to enable the default 50mv current-limit threshold. in adjustable mode, the current-limit threshold across csh1 and csl1 is precisely 1/10th the voltage seen at ilim1 over a 500mv to 2.0v range. the logic threshold for switchover to the 50mv default value is approximately v cc - 1v. ep ep ep exposed pad. connect exposed backside pad to analog ground.
max8716/max8717/max8757 interleaved high-efficiency, dual power-supply controllers for notebook computers ______________________________________________________________________________________ 13 v dd dh1 bst1 dl1 lx1 csh1 c bst2 0.1 f n h2 d l2 r cs2 7m ? l2 5.7 h c out2 150 f +5v bias power-good 1 power-good 2 n l2 c bst1 0.1 f n h1 n l1 r cs1 7m ? c out1 220 f d l1 l1 5.7 h d bst1 d bst2 c1 1 f +5v bias 3.3v pwm output input (v in ) see table 1 for component specifications. fb1 power ground analog ground max8716 max8717 max8757 c in (2) 10 f ref (300khz) skip1 skip2 ilim1 ilim2 bst2 lx2 dl2 *pgnd *agnd csh2 csl2 fb2 dh2 csl1 default current limit on1 on2 on off 5v pwm output v cc pgood1 r1 20 ? c2 1 f r2 100k ? pgood2 fsel ref r3 100k ? v cc pulse- skipping control v cc v cc v cc c ref 0.22 f max8717 and max8757 only *for the max8716 agnd and pgnd, refer to a single pin designated gnd. figure 1. standard application circuit
max8716/max8717/max8757 interleaved high-efficiency, dual power-supply controllers for notebook computers 14 ______________________________________________________________________________________ reference (ref) the 2v reference is accurate to ?.5% over tempera- ture and load, making ref useful as a precision system reference. bypass ref to gnd with a 0.1? or greater ceramic capacitor. the reference sources up to 50? and sinks 10? to support external loads. smps detailed description power-on reset (por) occurs when v cc rises above approximately 2v, resetting the undervoltage, overvolt- age, and thermal-shutdown fault latches. the por cir- cuit also ensures that the low-side drivers are driven high until the smps controllers are activated. the v cc input undervoltage-lockout (uvlo) circuitry inhibits switching if v cc is below the v cc uvlo threshold. an internal soft-start gradually increases the regulation voltage during startup to reduce the input surge cur- rents (see the startup waveforms in the typical operating characteristics ). smps enable controls (on1, on2) on1 and on2 provide independent control of output soft-start and soft-shutdown. this allows flexible control of startup and shutdown sequencing. the outputs can be started simultaneously, sequentially, or indepen- dently. to provide sequential startup, connect component 5a/300khz 5a/500khz input voltage v in = 7v to 24v v in = 7v to 24v c in input capacitor (2) 10?, 25v taiyo yuden tmk432bj106km (2) 10?, 25v taiyo yuden tmk432bj106km c out1 , output capacitor for 3.3v output 220?, 4v, 25m ? low-esr capacitor sanyo 4tpe220m 150?, 4v, 25m ? low-esr capacitor sanyo 4tpe150m c out2 , output capacitor for 5v output 150?, 6.3v, 25m ? low-esr capacitor sanyo 6tpe150m 100?, 6.3v, 25m ? low-esr capacitor sanyo 6tpe100m n h_ high-side mosfet fairchild semiconductor fds6612a, international rectifier irf7807v fairchild semiconductor fds6612a, international rectifier irf7807v n l_ low-side mosfet fairchild semiconductor fds6670s, international rectifier irf7807vd1 fairchild semiconductor fds6670s, international rectifier irf7807vd1 d l_ schottky rectifier (if needed) nihon ec21qs03l 2a, 30v, 0.45v f nihon ec21qs03l 2a, 30v, 0.45v f l_ inductor 5.7? sumida cdep105-5r7nc 3.9? sumida cdrh124-3r9nc r sense_ 7m ? ?%, 0.5w resistor irc lr2010-01-r007f or dale wsl-2010-r007f 7m ? ?%, 0.5w resistor irc lr2010-01-r007f or dale wsl-2010-r007f table 1. component selection for standard applications supplier website avx www.avx.com central semiconductor www.centralsemi.com coilcraft www.coilcraft.com coiltronics www.coiltronics.com fairchild semiconductor www.fairchildsemi.com international rectifier www.irf.com kemet www.kemet.com panasonic www.panasonic.com/industrial sanyo www.secc.co.jp sumida www.sumida.com taiyo yuden www.t-yuden.com tdk www.component.tdk.com toko www.tokoam.com vishay (dale, siliconix) www.vishay.com table 2. component suppliers
max8716/max8717/max8757 interleaved high-efficiency, dual power-supply controllers for notebook computers ______________________________________________________________________________________ 15 on_ of one regulator to pgood_ of the other. for example, with on1 connected to pgood2, out1 soft- starts after out2 is in regulation. drive on_ low to clear the overvoltage, undervoltage, and thermal fault latches. soft-start and soft-shutdown soft-start begins when on_ is driven high and ref is in regulation. during soft-start, the output is ramped up from 0v to the final set voltage in 2ms. this reduces inrush current and provides a predictable ramp-up time for power sequencing. soft-shutdown begins after on_ goes low, an output undervoltage fault occurs, or a thermal fault occurs. fb1 dh1 bst1 dl1 lx1 pwm1 controller (figure 3) pgnd fb decode (figure 5) fsel ilim1 csh1 csl1 pgood1 power-good and fault protection (figure 7) internal fb fault osc max8717/max8757 v cc ref r r 2.0v ref gnd fb2 dh2 bst2 dl2 v dd lx2 pwm2 controller (figure 3) fb decode (figure 5) ilim2 csh2 csl2 pgood2 power-good and fault protection (figure 7) internal fb fault skip1 on1 skip2 on2 v dd figure 2. functional diagram
max8716/max8717/max8757 interleaved high-efficiency, dual power-supply controllers for notebook computers 16 ______________________________________________________________________________________ the two outputs are independent. a fault at one output does not trigger shutdown of the other. during soft- shutdown the output is ramped down to 0v in 4ms, reducing negative inductor currents that can cause negative voltages on the output. at the end of soft-shut- down, dl_ is driven high until startup is again triggered by a rising edge of on_. the reference is turned off when both outputs have been shut down. fixed-frequency, current-mode pwm controller the heart of each current-mode pwm controller is a multi-input, open-loop comparator that sums two sig- nals: the output-voltage error signal with respect to the reference voltage and the slope-compensation ramp (figure 3). the max8716/max8717/max8757 use a direct-summing configuration, approaching ideal cycle-to-cycle control over the output voltage without a traditional error amplifier and the phase shift associated with it. the max8716/max8717/max8757 use a rela- tively low loop gain, allowing the use of low-cost output capacitors. the low loop gain results in the 0.1% typical load-regulation error and helps reduce the output capacitor size and cost by shifting the unity-gain crossover frequency to a lower level. frequency selection (fsel) the fsel input selects the pwm mode switching fre- quency. table 3 shows the switching frequency based on the fsel connection. high-frequency (500khz) operation optimizes the application for the smallest component size, trading off efficiency due to higher switching losses. this may be acceptable in ultra- portable devices where the load currents are lower. low-frequency (200khz) operation offers the best over- all efficiency at the expense of component size and board space. forced-pwm mode to maintain low-noise fixed-frequency operation, drive skip _ high to put the output into forced-pwm mode. this disables the zero-crossing comparator and allows negative inductor current. during forced-pwm mode, the switching frequency remains constant and the no- load supply current is typically between 8ma and 20ma per phase, depending on external mosfets and switching frequency. light-load operation control ( skip_ ) the max8716/max8717/max8757 include skip _ inputs that enable the corresponding outputs to oper- ate in discontinuous mode. connect skip _ to gnd or ref as shown in table 4 to enable or disable the zero- crossing comparators of either controller. when the zero-crossing comparator is enabled, the controller forces dl_ low when the current-sense inputs detect zero inductor current. this keeps the inductor from dis- charging the output capacitors and forces the con- troller to skip pulses under light-load conditions to avoid overcharging the output. during skip mode, the v dd current consumption is reduced and efficiency is improved. during low-noise skip mode, the no-load rip- ple amplitude is two times smaller and the no-load switching frequency is four times higher, although the light-load efficiency is somewhat lower. idle-mode current-sense threshold when pulse-skipping mode is enabled, the on-time of the step-down controller terminates when the output voltage exceeds the feedback threshold and when the current-sense voltage exceeds the idle-mode current- sense threshold. under light-load conditions, the on- time duration depends solely on the idle-mode current-sense threshold, which is 20% ( skip _ = gnd) of the full-load current-limit threshold set by ilim_, or the low-noise current-sense threshold, which is 10% ( skip _ = ref) of the full-load current-limit threshold set by ilim_. this forces the controller to source a mini- mum amount of power with each cycle. to avoid over- charging the output, another on-time cannot begin until output voltage drops below the feedback threshold. since the zero-crossing comparator prevents the switching regulator from sinking current, the controller must skip pulses. therefore, the controller regulates the valley of the output ripple under light-load conditions. automatic pulse-skipping crossover in skip mode, an inherent automatic switchover to pfm takes place at light loads (figure 4). this switchover is affected by a comparator that truncates the low-side switch on-time at the inductor current? zero crossing. the zero-crossing comparator senses the inductor cur- rent across csh_ and csl_. once v csh - v csl _ drops below the 3mv zero-crossing, current-sense threshold, the comparator forces dl_ low (figure 3). this mecha- nism causes the threshold between pulse-skipping pfm and nonskipping pwm operation to coincide with the boundary between continuous and discontinuous inductor-current operation (also known as the ?ritical fsel switching frequency (khz) v cc 500 ref 300 gnd 200 table 3. fsel configuration table
max8716/max8717/max8757 interleaved high-efficiency, dual power-supply controllers for notebook computers ______________________________________________________________________________________ 17 conduction?point). the load-current level at which pfm/pwm crossover occurs, i load(skip) , is deter- mined by: the switching waveforms may appear noisy and asyn- chronous when light loading causes pulse-skipping operation, but this is a normal operating condition that results in high light-load efficiency. trade-offs in pfm noise vs. light-load efficiency are made by varying the inductance. generally, low inductance produces a broader efficiency vs. load curve, while higher values result in higher full-load efficiency (assuming that the i vv v lv load skip in out out in osc () () = ? ? 2 s r q r s q dh driver dl driver slope comp osc fb ref / 2 -1.2 x v limit agnd skip v limit 3mv csl csh soft-start soft-stop on skip decode 0.1 x v limit 0.05 x v limit figure 3. pwm-controller functional diagram
max8716/max8717/max8757 interleaved high-efficiency, dual power-supply controllers for notebook computers 18 ______________________________________________________________________________________ coil resistance remains fixed) and less output voltage ripple. penalties for using higher inductor values include larger physical size and degraded load-tran- sient response (especially at low input-voltage levels). output voltage dc output accuracy specifications in the electrical characteristics refer to the error comparator? thresh- old. when the inductor continuously conducts, the t on(skip) = v out v in x f osc inductor current i load(skip) time on-time 0 i load = i load(skip) 2 figure 4. pulse-skipping/discontinuous crossover point skip_ mode comments v cc forced-pwm mode fixed-frequency operation. constant output ripple voltage. able to source and sink current. gnd skip mode high efficiency at light loads. source-only applications. ref low-noise skip mode good efficiency at light loads. two times smaller no-load ripple and 4 times higher frequency compared with skip mode. source-only applications. table 4. skip_ configuration table mode condition comment power-up v cc uvlo dl_ tracks v cc as v cc rises from 0v to +5v. when on_ is low, dl_ tracks v cc as v cc falls. when on_ is high, dl_ is forced low as v cc falls below the 3.95v (typ) falling uvlo threshold. dl_ is forced high when v cc falls below 1v (typ). run on1 or on2 enabled normal operation. output overvoltage (ovp) protection either output > 115% of nominal level when the overvoltage (ov) comparator trips, the faulted side sets the ov latch, forcing pgood_ low and dl_ high. the other controller is not affected. the ov latch is cleared by cycling v cc below 1v or cycling the respective on_ pin. output undervoltage protection (uvp) either output < 70% of nominal level, uvp is enabled 6144 clock cycles (1/f osc ) after the output is enabled (on_ going high) when the undervoltage (uv) comparator trips, the faulted side sets the uv latch, forcing pgood_ low and initiating the soft-shutdown sequence by pulsing only dl_. dl_ goes high after soft-shutdown. the other controller is not affected. the uv latch is cleared by cycling v cc below 1v or cycling the respective on_ pin. shutdown on1 and on2 are driven low dl_ stays high after soft-shutdown is completed. all circuitry is shut down. thermal shutdown t j > +160? exited by por or cycling on1 and on2. dl1 and dl2 remain high. table 5. operating modes truth table
max8716/max8717/max8757 interleaved high-efficiency, dual power-supply controllers for notebook computers ______________________________________________________________________________________ 19 max8716/max8717/max8757 regulate the peak of the output ripple, so the actual dc output voltage is lower than the slope-compensated trip level by 50% of the output ripple voltage. for pwm operation (continuous conduction), the output voltage is accurately defined by the following equation: where v nom is the nominal output voltage, a slope equals 1%, and v ripple is the output ripple voltage (v ripple = r esr x ? i inductor as described in the output capacitor selection section). in discontinuous conduction (i out < i load(skip) ), the max8716/max8717/max8757 regulate the valley of the output ripple, so the output voltage has a dc regulation level higher than the error-comparator threshold. for pfm operation (discontinuous conduction), the output voltage is approximately defined by the following equation: where v nom is the nominal output voltage, f osc is the maximum switching frequency set by the internal oscil- lator, f sw is the actual switching frequency, and i idle is the idle-mode inductor current when pulse skipping. adjustable/fixed output voltages (dual-mode feedback) connect fb1 and fb2 to v cc to enable the fixed smps output voltages (3.3v and 5v, respectively), set by a preset, internal resistive voltage-divider connected between csl_ and analog ground. see figure 5. connect a resistive voltage-divider at fb_ between csl_ and gnd to adjust the respective output voltage between 1v and 5.5v. choose r2 (resistance from fb to agnd) to be approximately 10k ? and solve for r1 (resistance from out to fb) using the equation: where v fb_ = 1v nominal. current-limit protection (ilim_) the current-limit circuit uses differential current-sense inputs (csh_ and csl_) to limit the peak inductor cur- rent. if the magnitude of the current-sense signal exceeds the current-limit threshold, the pwm controller turns off the high-side mosfet (figure 3). at the next rising edge of the internal oscillator, the pwm controller does not initiate a new cycle unless the current-sense signal drops below the current-limit threshold. the actual maximum load current is less than the peak cur- rent-limit threshold by an amount equal to half of the inductor ripple current. therefore, the maximum load capability is a function of the current-sense resistance, inductor value, switching frequency, and duty cycle (v out / v in ). in forced-pwm mode, the max8716/max8717/ max8757 also implement a negative current limit to prevent excessive reverse inductor currents when v out is sinking current. the negative current-limit threshold is set to approximately -120% of the positive current limit and tracks the positive current limit when ilim is adjusted. connect ilim_ to v cc for the 50mv default threshold, or adjust the current-limit threshold with an external resis- tor-divider at ilim_. use a 2? to 20? divider current for accuracy and noise immunity. the current-limit threshold adjustment range is from 50mv to 200mv. in the adjustable mode, the current-limit threshold voltage equals precisely 1/10 the voltage seen at ilim_. the logic threshold for switchover to the 50mv default value is approximately v cc - 1v. carefully observe the pc board layout guidelines to ensure that noise and dc errors do not corrupt the dif- ferential current-sense signals seen by csh_ and csl_. place the ic close to the sense resistor with short, direct traces, making a kelvin-sense connection to the current-sense resistor. mosfet gate drivers (dh_, dl_) the dh_ and dl_ drivers are optimized for driving moderate-sized high-side, and larger low-side power mosfets. this is consistent with the low duty factor seen in notebook applications, where a large v in - v out differential exists. the high-side gate drivers (dh_) source and sink 2a, and the low-side gate dri- vers (dl_) source 1.7a and sink 3.3a. this ensures robust gate drive for high-current applications. the dh_ floating high-side mosfet drivers are powered by diode-capacitor charge pumps at bst_ (figure 6) while the dl_ synchronous-rectifier drivers are powered directly by the external 5v supply (v dd ). adaptive dead-time circuits monitor the dl_ and dh_ drivers and prevent either fet from turning on until the other is fully off. the adaptive driver dead-time allows operation without shoot-through with a wide range of mosfets, minimizing delays and maintaining efficien- cy. there must be a low-resistance, low-inductance path from the dl_ and dh_ drivers to the mosfet rr v v out fb 12 1 = ? ? ? ? ? ? ? _ _ vv ir out pfm nom sw osc idle esr () =+ ? ? ? ? ? ? ? ? 1 2 vv avv v v out pwm nom slope in nom in ripple () () = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 2
max8716/max8717/max8757 interleaved high-efficiency, dual power-supply controllers for notebook computers 20 ______________________________________________________________________________________ gates for the adaptive dead-time circuits to work prop- erly; otherwise, the sense circuitry in the max8716/ max8717/max8757 interprets the mosfet gates as ?ff?while charge actually remains. use very short, wide traces (50 mils to 100 mils wide if the mosfet is 1in from the driver). the internal pulldown transistor that drives dl_ low is robust, with a 0.6 ? (typ) on-resistance. this helps pre- vent dl_ from being pulled up due to capacitive cou- pling from the drain to the gate of the low-side mosfets when the inductor node (lx_) quickly switches from ground to v in . applications with high input voltages and long inductive driver traces may require additional gate- to-source capacitance to ensure fast-rising lx_ edges do not pull up the low-side mosfets gate, causing shoot-through currents. the capacitive coupling between lx_ and dl_ created by the mosfet? gate-to- drain capacitance (c rss ), gate-to-source capacitance (c iss - c rss ), and additional board parasitics should not exceed the following minimum threshold: variation of the threshold voltage may cause problems in marginal designs. alternatively, adding a resistor less than 10 ? in series with bst_ may remedy the problem by increasing the turn-on time of the high-side mosfet without degrading the turn-off time (figure 6). power-good output (pgood_) pgood_ is the open-drain output of a comparator that continuously monitors each smps output voltage for overvoltage and undervoltage conditions. pgood_ is actively held low in shutdown (on_ = gnd), soft-start, and soft-shutdown. once the analog soft-start termi- nates, pgood_ becomes high impedance as long as the output is above 90% of the nominal regulation volt- age set by fb_. pgood_ goes low once the output drops 10% below its nominal regulation point, an output overvoltage fault occurs, or on_ is pulled low. for a logic-level pgood_ output voltage, connect an exter- nal pullup resistor between pgood_ and +5v or +3.3v. a 100k ? pullup resistor works well in most applications. fault protection output overvoltage protection (max8716/max8717 only) if the output voltage of either smps rises above 115% of its nominal regulation voltage, the corresponding controller sets its overvoltage fault latch, pulls pgood_ low, and forces dl_ high for the corresponding smps controller. the other controller is not affected. if the condition that caused the overvoltage persists (such as a shorted high-side mosfet), the battery fuse will blow. cycle v cc below 1v or toggle on_ to clear the overvoltage fault latch and restart the smps controller. vv c c gs th in rss iss () > ? ? ? ? ? ? csl to error amplifier fb 2v fixed output fb = v cc adjustable output figure 5. dual-mode feedback decoder max8716 max8717 max8757 v dd bst dh lx (r bst )* (c nl )* d bst c bst c byp input (v in ) n h l dl pgnd n l (r bst )* optional?he resistor lowers emi by decreasing the switching-node rise time. (c nl )* optional?he capacitor reduces lx to dl capacitive coupling that can cause shoot-through currents. v dd figure 6. optional gate-driver circuitry
max8716/max8717/max8757 interleaved high-efficiency, dual power-supply controllers for notebook computers ______________________________________________________________________________________ 21 output undervoltage protection if the output voltage of either smps falls below 70% of its regulation voltage, the corresponding controller sets its undervoltage fault latch, pulls pgood_ low, and begins soft-shutdown for the corresponding smps con- troller by pulsing dl_. dh_ remains off during the soft- shutdown sequence initiated by an unvervoltage fault. the other controller is not affected. after soft-shutdown has completed, the max8716/max8717/max8757 force dl_ high and dh_ low. cycle v cc below 1v or toggle on_ to clear the undervoltage fault latch and restart the smps controller. v cc por and uvlo power-on reset (por) occurs when v cc rises above approximately 2v, resetting the fault latch and prepar- ing the pwm for operation. v cc undervoltage-lockout (uvlo) circuitry inhibits switching, forces pgood_ low, and forces the dl_ gate drivers low. if v cc drops low enough to trip the uvlo comparator while on_ is high, the max8716/max8717/max8757 immediately force dh_ and dl_ low on both controllers. the output discharges to 0v at a rate dependent on the load and the total output capacitance. this prevents negative output voltages, eliminating the need for a schottky diode to gnd at the output. thermal fault protection the max8716/max8717/max8757 feature a thermal fault-protection circuit. when the junction temperature rises above +160?, a thermal sensor sets the fault latches, pulls pgood low, and shuts down both smps controllers using the soft-shutdown sequence (see the sort-start and soft-shutdown section). cycle v cc below 1v or toggle on1 and on2 to clear the fault latches and restart the controllers after the junction temperature cools by 15?. design procedure firmly establish the input voltage range and maximum load current before choosing a switching frequency and inductor operating point (ripple-current ratio). the primary design trade-off lies in choosing a good switch- ing frequency and inductor operating point, and the fol- lowing four factors dictate the rest of the design: ? input voltage range. the maximum value (v in(max) ) must accommodate the worst-case, high ac-adapter voltage. the minimum value (v in(min) ) must account for the lowest battery voltage after drops due to con- nectors, fuses, and battery selector switches. if there is a choice at all, lower input voltages result in better efficiency. ? maximum load current. there are two values to consider. the peak load current (i load(max) ) deter- mines the instantaneous component stresses and fil- tering requirements and thus drives output capacitor selection, inductor saturation rating, and the design of the current-limit circuit. the continuous load cur- rent (i load ) determines the thermal stresses and thus drives the selection of input capacitors, mosfets, and other critical heat-contributing com- ponents. ? switching frequency. this choice determines the basic trade-off between size and efficiency. the optimal frequency is largely a function of maximum input voltage, due to mosfet switching losses that are proportional to frequency and v in 2 . the opti- mum frequency is also a moving target, due to rapid improvements in mosfet technology that are mak- ing higher frequencies more practical. ? inductor operating point. this choice provides trade-offs between size vs. efficiency and transient response vs. output ripple. low inductor values pro- vide better transient response and smaller physical size, but also result in lower efficiency and higher output ripple due to increased ripple currents. the minimum practical inductor value is one that causes the circuit to operate at the edge of critical conduc- tion (where the inductor current just touches zero with every cycle at maximum load). inductor values power- good fault 0.9 x int ref_ 1.15 x int ref_ 0.7 x int ref_ fault latch power-good fault protection internal fb timer por figure 7. power-good and fault protection
max8716/max8717/max8757 interleaved high-efficiency, dual power-supply controllers for notebook computers 22 ______________________________________________________________________________________ lower than this grant no further size-reduction bene- fit. the optimum operating point is usually found between 20% and 50% ripple current. when pulse- skipping ( skip low and light loads), the inductor value also determines the load-current value at which pfm/pwm switchover occurs. inductor selection the switching frequency and inductor operating point determine the inductor value as follows: for example: i load(max) = 5a, v in = 12v, v out = 5v, f osc = 300khz, 30% ripple current or lir = 0.3: find a low-loss inductor having the lowest possible dc resistance that fits in the allotted dimensions. most inductor manufacturers provide inductors in standard values, such as 1.0?, 1.5?, 2.2?, 3.3?, etc. also look for nonstandard values, which can provide a better compromise in lir across the input voltage range. if using a swinging inductor (where the no-load induc- tance decreases linearly with increasing current), evalu- ate the lir with properly scaled inductance values. for the selected inductance value, the actual peak-to-peak inductor ripple current ( ? i inductor ) is defined by: ferrite cores are often the best choice, although pow- dered iron is inexpensive and can work well at 200khz. the core must be large enough not to saturate at the peak inductor current (i peak ): transient response the inductor ripple current also impacts transient- response performance, especially at low v in - v out dif- ferentials. low inductor values allow the inductor current to slew faster, replenishing charge removed from the output filter capacitors by a sudden load step. the total output voltage sag is the sum of the voltage sag while the inductor is ramping up and the voltage sag before the next pulse can occur: where d max is maximum duty factor (see the electrical characteristics ), t is the switching period (1 / f osc ), and ? t equals v out / v in x t when in pwm mode, or l x 0.2 x i max / (v in - v out ) when in skip mode. the amount of overshoot during a full-load to no-load transient due to stored inductor energy can be calculated as: setting the current limit the minimum current-limit threshold must be great enough to support the maximum load current when the current limit is at the minimum tolerance value. the peak inductor current occurs at i load(max) plus half the ripple current; therefore: where i limit_ equals the minimum current-limit thresh- old voltage divided by the current-sense resistance (r sense ). for the 50mv default setting, the minimum current-limit threshold is 50mv. connect ilim_ to v cc for a default 50mv current-limit threshold. in adjustable mode, the current-limit thresh- old is precisely 1/10 the voltage seen at ilim_. for an adjustable threshold, connect a resistive divider from ref to analog ground (gnd) with ilim_ connected to the center tap. the external 500mv to 2v adjustment range corresponds to a 50mv to 200mv current-limit threshold. when adjusting the current limit, use 1% tol- erance resistors and a divider current of approximately 10? to prevent significant inaccuracy in the current- limit tolerance. the current-sense method (figure 8) and magnitude determines the achievable current-limit accuracy and power loss. typically, higher current-sense limits pro- vide tighter accuracy, but also dissipate more power. most applications employ a current-limit threshold (v lim ) of 50mv to 100mv, so the sense resistor can be determined by: r sense_ = v lim_ / i lim_ for the best current-sense accuracy and overcurrent protection, use a 1% tolerance current-sense resistor between the inductor and output as shown in figure 8a. ii i limit load max inductor >+ ? ? ? ? ? ? () ? 2 v il cv soar load max out out () () ? 2 2 v li cvd v itt c sag load max out in max out load max out = ? + ? () () () () () ??? 2 2 ii i peak load max inductor =+ () ? 2 ? i vvv vl inductor out in out in osc = ? ? () l vvv v khz a h = ? = 5125 12 300 5 0 3 650 () . . l vvv v i lir out in out in osc load max = ? ? () ()
max8716/max8717/max8757 interleaved high-efficiency, dual power-supply controllers for notebook computers ______________________________________________________________________________________ 23 this configuration constantly monitors the inductor cur- rent, allowing accurate current-limit protection. alternatively, high-power applications that do not require highly accurate current-limit protection may reduce the overall power dissipation by connecting a series rc circuit across the inductor (figure 8b) with an equivalent time constant: where r l is the inductor? series dc resistance. in this configuration, the current-sense resistance equals the inductor? dc resistance (r sense = r l ). use the worst- case inductance and r l values provided by the induc- tor manufacturer, adding some margin for the inductance drop over temperature and load. output capacitor selection the output filter capacitor must have low enough equiv- alent series resistance (esr) to meet output ripple and load-transient requirements, yet have high enough esr to satisfy stability requirements. the output capaci- tance must be high enough to absorb the inductor energy while transitioning from full-load to no-load con- ditions without tripping the overvoltage fault protection. when using high-capacitance, low-esr capacitors (see the output-capacitor stability considerations section), the filter capacitor? esr dominates the output voltage ripple. so the output capacitor? size depends on the maximum esr required to meet the output-voltage-rip- ple (v ripple(p-p) ) specifications: v ripple(p-p) = r esr i load(max) lir in idle mode, the inductor current becomes discontinu- ous, with peak currents set by the idle-mode current- l r cr l eq eq = max8716 max8717 max8757 c out input (v in ) inductor c in b) lossless inductor sensing csl_ csh_ pgnd dl_ dh_ lx_ c eq r eq r bias = r eq max8716 max8717 max8757 c out input (v in ) n h n l n h n l l c in d l d l a) output series resistor sensing pgnd dl_ dh_ lx_ csl_ csh_ r sense figure 8. current-sense configurations
max8716/max8717/max8757 interleaved high-efficiency, dual power-supply controllers for notebook computers 24 ______________________________________________________________________________________ sense threshold (v idle = 0.2v limit ). in idle mode, the no-load output ripple can be determined as follows: the actual capacitance value required relates to the physical size needed to achieve low esr, as well as to the chemistry of the capacitor technology. thus, the capacitor is usually selected by esr and voltage rating rather than by capacitance value (this is true of tanta- lums, os-cons, polymers, and other electrolytics). when using low-capacity filter capacitors, such as ceramic capacitors, size is usually determined by the capacity needed to prevent v sag and v soar from causing problems during load transients. generally, once enough capacitance is added to meet the over- shoot requirement, undershoot at the rising load edge is no longer a problem (see the v sag and v soar equa- tions in the transient response section). however, low- capacity filter capacitors typically have high-esr zeros that may effect the overall stability (see the output- capacitor stability considerations section). output-capacitor stability considerations stability is determined by the value of the esr zero rel- ative to the switching frequency. the boundary of insta- bility is given by the following equation: where: for a typical 300khz application, the esr zero frequen- cy must be well below 95khz, preferably below 50khz. tantalum and os-con capacitors in widespread use at the time of publication have typical esr zero fre- quencies of 25khz. in the design example used for inductor selection, the esr needed to support 25mv p-p ripple is 25mv/1.5a = 16.7m ? . one 220?/4v sanyo polymer (tpe) capacitor provides 15m ? (max) esr. this results in a zero at 48khz, well within the bounds of stability. for low input-voltage applications where the duty cycle exceeds 50% (v out / v in 50%), the output ripple voltage should not be greater than twice the internal slope-compensation voltage: v ripple 0.02 x v out where v ripple equals ? i inductor x r esr . the worst- case esr limit occurs when v in = 2 x v out , so the above equation can be simplified to provide the follow- ing boundary condition: r esr 0.04 x l x osc do not put high-value ceramic capacitors directly across the feedback sense point without taking precau- tions to ensure stability. large ceramic capacitors can have a high-esr zero frequency and cause erratic, unstable operation. however, it is easy to add enough series resistance by placing the capacitors a couple of inches downstream from the feedback sense point, which should be as close as possible to the inductor. unstable operation manifests itself in two related but distinctly different ways: short/long pulses or cycle skipping resulting in a lower switching frequency. instability occurs due to noise on the output or because the esr is so low that there is not enough voltage ramp in the output voltage signal. this ?ools?the error com- parator into triggering too early or skipping a cycle. cycle skipping is more annoying than harmful, resulting in nothing worse than increased output ripple. however, it can indicate the possible presence of loop instability due to insufficient esr. loop instability can result in oscillations at the output after line or load steps. such perturbations are usually damped, but can cause the output voltage to rise above or fall below the tolerance limits. the easiest method for checking stability is to apply a very fast zero-to-max load transient and carefully observe the output-voltage-ripple envelope for over- shoot and ringing. it can help to simultaneously monitor the inductor current with an ac current probe. do not allow more than one cycle of ringing after the initial step-response under/overshoot. input capacitor selection the input capacitor must meet the ripple-current requirement (i rms ) imposed by the switching currents. for an out-of-phase regulator, the total rms current in the input capacitor is a function of the load currents, the input currents, the duty cycles, and the amount of overlap as defined in figure 9. the 40/60 optimal interleaved architecture of the max8716/max8717/max8757 allows the input voltage to go as low as 8.3v before the duty cycles begin to overlap. this offers improved efficiency over a regular 180 out-of-phase architecture where the duty cycles begin to overlap below 10v. figure 9 shows the input- capacitor rms current vs. input voltage for an applica- tion that requires 5v/5a and 3.3v/5a. this shows the improvement of the 40/60 optimal interleaving over 50/50 interleaving and in-phase operation. ?= esr esr out rc 1 2 ? ? esr sw v vr r ripple p p idle esr sense () ? =
max8716/max8717/max8757 interleaved high-efficiency, dual power-supply controllers for notebook computers ______________________________________________________________________________________ 25 for most applications, nontantalum chemistries (ceram- ic, aluminum, or os-con) are preferred due to their resistance to power-up surge currents typical of sys- tems with a mechanical switch or connector in series with the input. choose a capacitor that has less than 10? temperature rise at the rms input current for opti- mal reliability and lifetime. power mosfet selection most of the following mosfet guidelines focus on the challenge of obtaining high load-current capability when using high-voltage (>20v) ac adapters. low-cur- rent applications usually require less attention. the high-side mosfet (n h ) must be able to dissipate the resistive losses plus the switching losses at both v in(min) and v in(max) . ideally, the losses at v in(min) should be roughly equal to the losses at v in(max) , with lower losses in between. if the losses at v in(min) are significantly higher, consider increasing the size of n h . conversely, if the losses at v in(max) are significantly higher, consider reducing the size of n h . if v in does not vary over a wide range, optimum efficiency is achieved by selecting a high-side mosfet (n h ) that has conduction losses equal to the switching losses. choose a low-side mosfet (n l ) that has the lowest possible on-resistance (r ds(on) ), comes in a moder- ate-sized package (i.e., 8-pin so, dpak, or d 2 pak), and is reasonably priced. ensure that the max8716/max8717/max8757 dl_ gate driver can sup- ply sufficient current to support the gate charge and the current injected into the parasitic drain-to-gate capaci- tor caused by the high-side mosfet turning on; other- wise, cross-conduction problems may occur. switching losses are not an issue for the low-side mosfet since it is a zero-voltage switched device when used in the step-down topology. power mosfet dissipation worst-case conduction losses occur at the duty-factor extremes. for the high-side mosfet (n h ), the worst- case power dissipation due to resistance occurs at minimum input voltage: generally, use a small high-side mosfet to reduce switching losses at high input voltages. however, the r ds(on) required to stay within package power-dissi- pation limits often limits how small the mosfet can be. the optimum occurs when the switching losses equal the conduction (r ds(on) ) losses. high-side switching losses do not become an issue until the input is greater than approximately 15v. calculating the power dissipation in high-side mosfets (n h ) due to switching losses is difficult, since it must allow for difficult-to-quantify factors that influ- ence the turn-on and turn-off times. these factors include the internal gate resistance, gate charge, threshold voltage, source inductance, and pc board layout characteristics. the following switching-loss cal- culation provides only a very rough estimate and is no substitute for breadboard evaluation, preferably includ- ing verification using a thermocouple mounted on n h : where c oss is the n h , mosfet's output capacitance, q g(sw) 2 , is the change needed to turn on the n h mosfet, and i gate is the peak gate-drive source/sink current (1a typ). pd (n switching) vifq i cvf 2 h in(max) load sw total g(sw) gate oss in 2 sw = ? ? ? ? ? ? ? ? ? ? ? ? + pd n resistive v v ir h out in load ds on ()() () = 2 input capacitor rms current vs. input voltage v in (v) i rms (a) 18 16 12 14 10 8 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 620 in phase 5v/5a and 3.3v/5a 50/50 interleaving 40/60 optimal interleaving input rms current for interleaved operation input rms current for single-phase operation (i out1 - i in ) 2 (d lx1 - d ol ) + (i out2 - i in ) 2 (d lx2 - d ol ) + (i out1 + i out2 - i in ) 2 d ol + i in 2 (1 - d lx1 - d lx2 + d ol ) d lx1 = v out (v in - v out ) v in i rms = i load d ol = duty-cycle overlap fraction v out1 v in v out1 i out1 + v out2 i out2 v in d lx2 = v out2 v in ( ) i in = i rms = figure 9. input rms current
max8716/max8717/max8757 interleaved high-efficiency, dual power-supply controllers for notebook computers 26 ______________________________________________________________________________________ switching losses in the high-side mosfet can become a heat problem when maximum ac adapter voltages are applied, due to the squared term in the switching- loss equation (c x v in 2 x f sw ). if the high-side mosfet chosen for adequate r ds(on) at low battery voltages becomes extraordinarily hot when subjected to v in(max) , consider choosing another mosfet with lower parasitic capacitance. for the low-side mosfet (n l ), the worst-case power dissipation always occurs at maximum battery voltage: the absolute worst case for mosfet power dissipation occurs under heavy-overload conditions that are greater than i load(max) but are not high enough to exceed the current limit and cause the fault latch to trip. to protect against this possibility, ?verdesign?the cir- cuit to tolerate: where i limit is the peak current allowed by the current- limit circuit, including threshold tolerance and sense- resistance variation. the mosfets must have a relatively large heatsink to handle the overload power dissipation. choose a schottky diode (d l ) with a forward-voltage drop low enough to prevent the low-side mosfet? body diode from turning on during the dead time. as a general rule, select a diode with a dc current rating equal to 1/3rd of the load current. this diode is optional and can be removed if efficiency is not critical. boost capacitors the boost capacitors (c bst ) must be selected large enough to handle the gate-charging requirements of the high-side mosfets. typically, 0.1? ceramic capacitors work well for low-power applications driving medium-sized mosfets. however, high-current appli- cations driving large, high-side mosfets require boost capacitors larger than 0.1?. for these applications, select the boost capacitors to avoid discharging the capacitor more than 200mv while charging the high- side mosfets?gates: where q gate is the total gate charge specified in the high-side mosfet? data sheet. for example, assume the fds6612a n-channel mosfet is used on the high side. according to the manufacturer? data sheet, a sin- gle fds6612a has a maximum gate charge of 13nc (v gs = 5v). using the above equation, the required boost capacitance would be: selecting the closest standard value, this example requires a 0.1? ceramic capacitor. applications information duty-cycle limits minimum input voltage the minimum input operating voltage (dropout voltage) is restricted by the maximum duty-cycle specification (see the electrical characteristics table). for the best dropout performance, use the slowest switching-fre- quency setting (200khz, fsel = gnd). however, keep in mind that the transient performance gets worse as the step-down regulators approach the dropout volt- age, so bulk output capacitance must be added (see the voltage sag and soar equations in the design procedure section). the absolute point of dropout occurs when the inductor current ramps down during the off-time ( ? i down ) as much as it ramps up during the on-time ( ? i up ). this results in a minimum operating voltage defined by the following equation: where v chg and v dis are the parasitic voltage drops in the charge and discharge paths, respectively. a rea- sonable minimum value for h is 1.5, while the absolute minimum input voltage is calculated with h = 1. maximum input voltage the max8716/max8717/max8757 controller includes a minimum on-time specification, which determines the maximum input operating voltage that maintains the selected switching frequency (see the electrical characteristics table). operation above this maximum input voltage results in pulse-skipping operation, regardless of the operating mode selected by skip . at the beginning of each cycle, if the output voltage is still above the feedback threshold voltage, the controller does not trigger an on-time pulse, effectively skipping a cycle. this allows the controller to maintain regulation vvvh d vv in min out chg max out dis () () =++ ? ? ? ? ? ? ? + 1 1 c nc mv f bst == 13 100 0 065 . c q mv bst gate = 200 ii i load limit inductor = ? ? ? ? ? ? ? ? 2 pd n resistive v v ir l out in max load ds on () () () () = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 2
max8716/max8717/max8757 interleaved high-efficiency, dual power-supply controllers for notebook computers ______________________________________________________________________________________ 27 above the maximum input voltage, but forces the con- troller to effectively operate with a lower switching fre- quency. this results in an input threshold voltage at which the controller begins to skip pulses (v in(skip) ): where f osc is the switching frequency selected by fsel. pc board layout guidelines careful pc board layout is critical to achieving low switching losses and clean, stable operation. the switching power stage requires particular attention (figure 10). if possible, mount all the power compo- nents on the top side of the board, with their ground terminals flush against one another. follow these guide- lines for good pc board layout: keep the high-current paths short, especially at the ground terminals. this practice is essential for sta- ble, jitter-free operation. keep the power traces and load connections short. this practice is essential for high efficiency. using thick copper pc boards (2oz vs. 1oz) can enhance full-load efficiency by 1% or more. correctly routing pc board traces is a difficult task that must be approached in terms of fractions of centimeters, where a single m ? of excess trace resistance caus- es a measurable efficiency penalty. minimize current-sensing errors by connecting csh_ and csl_ directly across the current-sense resistor (r sense_ ). when trade-offs in trace lengths must be made, it is preferable to allow the inductor charging path to be made longer than the discharge path. for example, it is better to allow some extra distance between the input capacitors and the high-side mosfet than to allow distance between the inductor and the low- side mosfet or between the inductor and the out- put filter capacitor. route high-speed switching nodes (bst_, lx_, dh_, and dl_) away from sensitive analog areas (ref, fb_, csh_, csl_). layout procedure 1) place the power components first, with ground ter- minals adjacent (n l _ source, c in , c out _, and d l _ anode). if possible, make all these connections on the top layer with wide, copper-filled areas. 2) mount the controller ic adjacent to the low-side mosfet, preferably on the back side opposite n l_ and n h_ to keep lx_, gnd, dh_, and the dl_ gate- drive lines short and wide. the dl_ and dh_ gate traces must be short and wide (50 mils to 100 mils wide if the mosfet is 1in from the controller ic) to keep the driver impedance low and for proper adap- tive dead-time sensing. 3) group the gate-drive components (bst_ diode and capacitor and ldo5 bypass capacitor) together near the controller ic. 4) make the dc-dc controller ground connections as shown in figures 1 and 10. this diagram can be viewed as having two separate ground planes: power ground, where all the high-power compo- nents go; and an analog ground plane for sensitive analog components. the analog ground plane and power ground plane must meet only at a single point directly at the ic. 5) connect the output power planes directly to the out- put filter capacitor positive and negative terminals with multiple vias. place the entire dc-dc converter circuit as close to the load as is practical. chip information transistor count: 5879 process: bicmos vv t in skip out osc on min () () = ? ? ? ? ? ? ? 1
max8716/max8717/max8757 interleaved high-efficiency, dual power-supply controllers for notebook computers 28 ______________________________________________________________________________________ via to power ground max8717/max8757 top layer max8717/max8757 bottom layer via to ref bypass capacitor connect gnd and pgnd to the controller at one point only as shown connect the exposed pad to analog gnd inductor c out c out c in input kelvin-sense vias under the sense resistor (refer to the evaluation kit) ground output inductor c out input ground output dh lx dl high-power layout low-power layout dual n-channel mosfet single n-channel mosfets via to v cc pin via to v cc bypass capacitor via to ref pin c in figure 10. pc board layout example
max8716/max8717/max8757 interleaved high-efficiency, dual power-supply controllers for notebook computers ______________________________________________________________________________________ 29 package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) 24l qfn thin.eps package outline, 21-0139 2 1 e 12, 16, 20, 24, 28l thin qfn, 4x4x0.8mm package outline, 21-0139 2 2 e 12, 16, 20, 24, 28l thin qfn, 4x4x0.8mm
max8716/max8717/max8757 interleaved high-efficiency, dual power-supply controllers for notebook computers maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 30 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2005 maxim integrated products printed usa is a registered trademark of maxim integrated products, inc. max8716/max8717/max8757 package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) qfn thin.eps

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